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| rev.1.22 mar 30, 2007 page 1 of 53 rej03b0088-0122 m16c/30p group single-chip 16-bit cmos microcomputer rej03b0088-0122 rev.1.22 mar 30, 2007 1. overview the m16c/30p group of single-chip microcomputers is bu ilt using the high-performance silicon gate cmos process using a m16c/60 series cpu core and is p ackaged in a 100-pin plastic molded qfp. these single-chip microco mputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 1 mbyte of address space, they are capable of executing instruc tions at high speed. in addition, these microcomputers contain a multiplier and dmac which combined with fast instruction processing capability, make it suitable for control of various oa, communication, and indu strial equipment which requir es high-speed arithmetic/ logic operations. 1.1 applications audio, cameras, tv, home applia nce, office/communications/porta ble/industrial equipment, etc.
m16c/30p group 1. overview rev.1.22 mar 30, 2007 page 2 of 53 rej03b0088-0122 1.2 performance outline table 1.1 lists performance outline of m16c/30p group. notes: 1. i 2 c bus is a registered trademark of koninklijke philips electronics n. v. 2. iebus is a registered trademark of nec electronics corporation. 3. use the m16c/30p on vcc1 = vcc2. table 1.1 performance outline of m16c/30p group item performance cpu number of basic inst ructions 91 instructions minimum instruction execution time 62.5ns(f(xin)=16mhz, vcc1=vcc2=3.0 to 5.5v, no wait) 100ns(f(xin)=10mhz, vcc1=v cc2=2.7 to 5.5v, no wait) operation mode single-chip, memory expansion and microprocessor mode memory space 1 mbyte memory capacity see table 1.2 product list peripheral function port input/output : 87 pins, input : 1 pin multifunction timer timer a : 16 bits x 3 channels, timer b : 16 bits x 3 channels serial interface 1 channels clock synchronous, uart, i 2 cbus (1) , iebus (2) 2 channels clock synchronous, uart, i 2 cbus (1) a/d converter 10-bit a/d conver ter: 1 circuit, 18 channels dmac 2 channels crc calculation circuit ccitt-crc watchdog timer 15 bits x 1 channel (with prescaler) interrupt internal: 20 sources, external: 7 sources, software: 4 sources, priority level: 7 levels clock generating circuit 2 circuits main clock generation circuit (*), subclock generation circuit (*), (*)equipped with a built-in feedback resistor. electric characteristics supply voltage vcc1=vcc2=3.0 to 5.5 v (f(xin)=16mhz) vcc1=vcc2=2.7 to 5.5 v (f(xin)=10mhz, no wait) power consumption 10 ma (v cc1=vcc2=5v, f(xin)=16mhz) 8 ma (vcc1=vcc2=3v, f(xin)=10mhz) 1.8 a (vcc1=vcc2=3v, f(xcin)=32khz, wait mode) 0.7 a(vcc1=vcc2=3v, stop mode) one time flash version program supply voltage 3 .30.3 v or 5.00.5 v flash memory version program/erase supply voltage 3.30.3 v or 5.00.5 v program and erase endurance 100 times (all area) operating ambient temperature -20 to 85 c, -40 to 85 c package 100-pin plastic mold qfp, lqfp m16c/30p group 1. overview rev.1.22 mar 30, 2007 page 3 of 53 rej03b0088-0122 1.3 block diagram figure 1.1 is a m16c/30p group block diagram. figure 1.1 m16c/30p group block diagram output (timer a): 3 input (timer b): 3 internal peripheral functions watchdog timer (15 bits) dmac (2 channels) memory rom (1) ram (2) a/d converter (10 bits x 18 channels ) uart or clock synchronous serial i/o (3 channels) system clock generation circuit xin-xout xcin-xcout m16c/60 series16-bit cpu core port p0 8 port p1 8 port p2 8 8 8 8 port p6 8 8 r0l r0h r1h r1l r2 r3 a0 a1 fb sb isp usp intb crc arithmetic circuit (ccitt ) (polynomial : x 16 +x 12 +x 5 +1) multiplier 7 8 8 port p10 port p9 port p8_5 port p8 port p7 notes : 1. rom size depends on microcomputer type. 2. ram size depends on microcomputer type. port p5 port p4 port p3 pc flg timer (16-bit) m16c/30p group 1. overview rev.1.22 mar 30, 2007 page 4 of 53 rej03b0088-0122 1.4 product list table 1.2 lists the m16c/30p group products and figure 1.2 shows the part no., memory size, and package. table 1.4 lists product code of mask rom version for m16c /30p. figure 1.3 shows the marking diagram of mask rom version for m16c/30p (top view). table 1.5 lists product code of one time flash version, flash memory version, and rom-less version for m16c/30p. figure 1.4 s hows the marking diagram of one time flash version, flash memory version, and rom-less version for m 16c/30p (top view). please specify the marking for m16c30p (mask rom version) when placing an order for rom. (d): under development (p): under planning notes: 1. previous package codes are as follows. prqp0100jb-a : 100p6s-a, plqp0100kb-a : 100p6q-a 2. block a (4-kbytes space) is available in flash memory version. table 1.2 product list (1) as of march 2007 part no. rom capacity ram capacity package code (1) remarks m30302map-xxxfp 96 kbytes 5 kbytes prqp0100jb-a mask rom version m30302map-xxxgp plqp0100kb-a m30302mcp-xxxfp 128 kbytes prqp0100jb-a m30302mcp-xxxgp plqp0100kb-a m30302mdp-xxxfp 160 kbytes 6 kbytes prqp0100jb-a m30302mdp-xxxgp plqp0100kb-a m30302mep-xxxfp 192 kb ytes prqp0100jb-a m30302mep-xxxgp plqp0100kb-a m30302gapfp 96 kbytes 5 kbytes prqp0100jb-a one time flash version (blank product) m30302gapgp (d) plqp0100kb-a m30302gcpfp 128 kbytes prqp0100jb-a m30302gcpgp (d) plqp0100kb-a m30302gdpfp 160 kbytes 6 kbytes prqp0100jb-a m30302gdpgp (d) plqp0100kb-a m30304gdpfp (d) 12 kbytes prqp0100jb-a m30304gdpgp (d) plqp0100kb-a m30302gepfp 192 kbytes 6 kbytes prqp0100jb-a m30302gepgp (d) plqp0100kb-a m30304gepfp (d) 12 kbytes prqp0100jb-a m30304gepgp (d) plqp0100kb-a m30302ggpfp (d) 256 kbytes 12 kbytes prqp0100jb-a m30302ggpgp (d) plqp0100kb-a m30302gap-xxxfp 96 kbytes 5 kbytes prqp0100jb-a one time flash version (factory programmed product) m30302gapvgp (d) plqp0100kb-a m30302gcp-xxxfp 128 kbytes prqp0100jb-a m30302gcp-xxxgp (d) plqp0100kb-a m30302gdp-xxxfp 160 kbytes 6 kbytes prqp0100jb-a m30302gdp-xxxgp (d) plqp0100kb-a m30304gdp-xxxfp (d) 12 kbytes prqp0100jb-a m30304gdp-xxxgp (d) plqp0100kb-a m30302gep-xxxfp 192 kbytes 6 kbytes prqp0100jb-a m30302gep-xxxgp (d) plqp0100kb-a m30304gep-xxxfp (d) 12 kb ytes prqp0100jb-a m30304gep-xxxgp (d) plqp0100kb-a M30302GGP-XXXFP (d) 256 kbytes 12 kbytes prqp0100jb-a m30302ggp-xxxgp (d) plqp0100kb-a m16c/30p group 1. overview rev.1.22 mar 30, 2007 page 5 of 53 rej03b0088-0122 table 1.3 product list (2) as of march 2007 (d): under development (p): under planning notes: 1. previous package codes are as follows. prqp0100jb-a : 100p6s-a, plqp0100kb-a : 100p6q-a 2. block a (4-kbytes space) is available in flash memory version. figure 1.2 part no., memory size, and package part no. rom capacity ram capacity package code (1) remarks m30302fapfp 96 k + 4 kbytes 5 kb ytes prqp0100jb-a flash memory version (2) m30302fapgp plqp0100kb-a m30302fcpfp 128 k + 4 kbytes prqp0100jb-a m30302fcpgp plqp0100kb-a m30302fepfp 192 k + 4 kbytes 6 kbytes prqp0100jb-a m30302fepgp plqp0100kb-a m30302spfp - 6 kbytes prqp0100jb-a rom-less version m30302spgp plqp0100kb-a package type: fp : package prqp0100jb-a (100p6s-a) gp : package plqp0100kb-a (100p6q-a) rom no. memory type: m : mask rom version g : one time flash version f : flash memory version s : rom-less version part no. m 3 0 3 0 2 m e p - x x x h p shows ram capacity, pin count, etc (the value itself has no specific meaning) m16c/30 series m16c family rom capacity: a : 96 kbytes c : 128 kbytes d : 160 kbytes e : 192 kbytes g : 256 kbytes m16c/30p group m16c/30p group 1. overview rev.1.22 mar 30, 2007 page 6 of 53 rej03b0088-0122 figure 1.3 marking diagram of mask rom version for m16c/30p (top view) table 1.4 product code of mask rom version for m16c/30p product code package operat ing ambient temperature u1 lead-free -20 c to 85 c u4 -40 c to 85 c m1 6c m3 0 3 0 2 m d p - x x x f p a u1 xxxxxxx part no. (see figure 1.2 part no., memory size, and package ) chip version, product code and date code a : shows chip version. henceforth, whenever it changes a version, it continues with a, b, and c. u1 : shows product code. (see table 1.3 product code ) xxxxxxx : seven digits prqp0100jb-a (100p6s-a) 1. standard renesas mark m30302mdp - xxxfp au1 m16c xxxxxxx part no. (see figure 1.2 part no., memory size, and package ) chip version and product code a : shows chip version. henceforth, whenever it changes a version, it continues with a, b, and c. u1 : shows product code. (see table 1.3 product code ) date code seven digits 2. customer?s parts number + renesas catalog name m1 6c m30302mdp -xxxgp a u 1 xxxxxxx part no. (see figure 1.2 part no., memory size, and package ) chip version, product code and date code a : shows chip version. henceforth, whenever it changes a version, it continues with a, b, and c. u1 : shows product code. (see table 1.3 product code ) xxxxxxx : seven digits plqp0100kb-a (100p6q-a) 1. standard renesas mark m30302mdp a u 1 - xxxgp m1 6 c xxxxxxx part no. (see figure 1.2 part no., memory size, and package ) chip version and product code a : shows chip version. henceforth, whenever it changes a version, it continues with a, b, and c. u1 : shows product code. (see table 1.3 product code ) date code seven digits 2. customer?s parts number + renesas catalog name notes: 1. refer to the mark specification form for details of the mask rom version marking. m16c/30p group 1. overview rev.1.22 mar 30, 2007 page 7 of 53 rej03b0088-0122 notes:the one time flash version can be written once only. figure 1.4 marking diagram of one time flash version, flash memory version, and rom-less version for m16c/30p (top view) table 1.5 product code of one time flash version, flash memory version, and rom-less version for m16c/30p product code package internal rom operating ambient temperature program and erase endurance temperature range one time flash version u3 lead- free 0 0 c to 60 c -40 c to 85 c u5 -20 c to 85 c flash memory version u3 lead- free 100 0 c to 60 c -40 c to 85 c u5 -20 c to 85 c rom-less version u3 lead- free ?? -40 c to 85 c u5 -20 c to 85 c m1 6c m30302spfp au3 xxxxxxx part no. (see figure 1.2 part no., memory size, and package ) chip version and product code a : shows chip version. henceforth, whenever it changes a version, it continues with a, b, and c. u3 : shows product code. (see table 1.3 product code ) date code seven digits prqp0100jb-a (100p6s-a) m1 6c m30302spgp au3 xxxxxxx part no. (see figure 1.2 part no., memory size, and package ) chip version and product code a : shows chip version. henceforth, whenever it changes a version, it continues with a, b, and c. u3 : shows product code. (see table 1.3 product code ) date code seven digits plqp0100kb-a (100p6q-a) the product without marking of chip version of one time flash version, flash memory version, and the romless version corresponds to the chip version ?a?. m16c/30p group 1. overview rev.1.22 mar 30, 2007 page 8 of 53 rej03b0088-0122 1.5 pin configuration figures 1.5 to 1.6 show the pin configurations (top view). figure 1.5 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 p1_0/d8 p1_1/d9 p1_2/d10 p1_3/d11 p1_4/d12 vref avss vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p3_0/a8 p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 p7_4/ta2out p7_6 p5_6/ale p7_7 p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd vcc2 vss p5_7/rdy/clkout p4_5/cs1 p4_6/cs2 p4_7/cs3 avcc p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_3 p9_4 p9_5/anex0 p9_6/anex1 p9_1/tb1in p9_2/tb2in p8_0 p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p7_2/clk2/ta1out p8_2/int0 p7_1/rxd2/scl2/ta0in (1) p8_3/int1 p8_5/nmi p9_7/adtrg p4_4/cs0 p5_0/wrl/wr p5_1/wrh/bhe p9_0/tb0in p7_0/txd2/sda2/ta0out (1) p8_4/int2 p8_1 p7_3/cts2/rts2/ta1in p7_5/ta2in p1_5/d13/int3 p1_6/d14/int4 p1_7/d15 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 p2_0/a0 p2_1/a1 p2_2/a2 p2_3/a3 p2_4/a4 p2_5/a5 p2_6/a6 p2_7/a7 m16c/30p group package : prqp0100jb-a (100p6s-a) pin configuration (top view) notes: 1. p7_0 and p7_1 are n channel open-drain output pins. 2. use the m16c/30p on vcc1=vcc2. m16c/30p group 1. overview rev.1.22 mar 30, 2007 page 9 of 53 rej03b0088-0122 figure 1.6 pin configuration (top view) 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 p1_0/d8 p1_1/d9 p1_2/d10 p1_3/d11 p1_4/d12 vref avss p2_0/a0 p2_1/a1 p2_2/a2 p2_3/a3 p2_4/a4 p2_5/a5 p2_6/a6 p2_7/a7 p3_0/a8 p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 vcc2 vss avcc p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_5/anex0 p9_6/anex1 p9_7/adtrg p7_2/clk2/ta1out p7_1/rxd2/scl2/ta0in (1) p7_0/txd2/sda2/ta0out (1) p1_5/d13/int3 p1_6/d14/int4 p1_7/d15 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p7_4/ta2out p7_6 p7_7 p9_3 p9_4 p9_1/tb1in p9_2/tb2in p8_0 p8_2/int0 p8_3/int1 p8_5/nmi p9_0/tb0in p8_4/int2 p8_1 p7_3/cts2/rts2/ta1in p7_5/ta2in p5_6/ale p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd p5_7/clkout p4_5/cs1 p4_6/cs2 p4_7/cs3 p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p4_4/cs0 p5_0/wrl/wr p5_1/wrh/bhe m16c/30p group pin configuration (top view) package : plqp0100kb-a (100p6q-a) notes: 1. p7_0 and p7_1 are n channel open-drain output pins. 2. use the m16c/30p on vcc1=vcc2. m16c/30p group 1. overview rev.1.22 mar 30, 2007 page 10 of 53 rej03b0088-0122 table 1.6 pin characteristics (1) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin fp gp 1 99 p9_6 anex1 2 100 p9_5 anex0 3 1 p9_4 4 2 p9_3 5 3 p9_2 tb2in 6 4 p9_1 tb1in 7 5 p9_0 tb0in 8 6 byte 9 7 cnvss 10 8 xcin p8_7 11 9 xcout p8_6 12 10 reset 13 11 xout 14 12 vss 15 13 xin 16 14 vcc1 17 15 p8_5 nmi 18 16 p8_4 int2 19 17 p8_3 int1 20 18 p8_2 int0 21 19 p8_1 22 20 p8_0 23 21 p7_7 24 22 p7_6 25 23 p7_5 ta2in 26 24 p7_4 ta2out 27 25 p7_3 ta1in cts2 /rts2 28 26 p7_2 ta1out clk2 29 27 p7_1 ta0in rxd2/scl2 30 28 p7_0 ta0out txd2/sda2 31 29 p6_7 txd1/sda1 32 30 p6_6 rxd1/scl1 33 31 p6_5 clk1 34 32 p6_4 cts1 /rts1 /cts0 /clks1 35 33 p6_3 txd0/sda0 36 34 p6_2 rxd0/scl0 37 35 p6_1 clk0 38 36 p6_0 cts0 /rts0 39 37 p5_7 rdy /clkout 40 38 p5_6 ale 41 39 p5_5 hold 42 40 p5_4 hlda 43 41 p5_3 bclk 44 42 p5_2 rd 45 43 p5_1 wrh /bhe 46 44 p5_0 wrl /wr 47 45 p4_7 cs3 48 46 p4_6 cs2 49 47 p4_5 cs1 50 48 p4_4 cs0 m16c/30p group 1. overview rev.1.22 mar 30, 2007 page 11 of 53 rej03b0088-0122 table 1.7 pin characteristics (2) pin no. control pin port interrupt pin timer pin uart pin analog pin bus control pin fp gp 51 49 p4_3 a19 52 50 p4_2 a18 53 51 p4_1 a17 54 52 p4_0 a16 55 53 p3_7 a15 56 54 p3_6 a14 57 55 p3_5 a13 58 56 p3_4 a12 59 57 p3_3 a11 60 58 p3_2 a10 61 59 p3_1 a9 62 60 vcc2 63 61 p3_0 a8 64 62 vss 65 63 p2_7 a7 66 64 p2_6 a6 67 65 p2_5 a5 68 66 p2_4 a4 69 67 p2_3 a3 70 68 p2_2 a2 71 69 p2_1 a1 72 70 p2_0 a0 73 71 p1_7 d15 74 72 p1_6 int4 d14 75 73 p1_5 int3 d13 76 74 p1_4 d12 77 75 p1_3 d11 78 76 p1_2 d10 79 77 p1_1 d9 80 78 p1_0 d8 81 79 p0_7 an0_7 d7 82 80 p0_6 an0_6 d6 83 81 p0_5 an0_5 d5 84 82 p0_4 an0_4 d4 85 83 p0_3 an0_3 d3 86 84 p0_2 an0_2 d2 87 85 p0_1 an0_1 d1 88 86 p0_0 an0_0 d0 89 87 p10_7 ki3 an7 90 88 p10_6 ki2 an6 91 89 p10_5 ki1 an5 92 90 p10_4 ki0 an4 93 91 p10_3 an3 94 92 p10_2 an2 95 93 p10_1 an1 96 94 avss 97 95 p10_0 an0 98 96 vref 99 97 avcc 100 98 p9_7 adtrg m16c/30p group 1. overview rev.1.22 mar 30, 2007 page 12 of 53 rej03b0088-0122 1.6 pin description i : input o : output i/o : input and output table 1.8 pin description (1) signal name pin name i/o type description power supply input vcc1, vcc2 vss i apply 2.7 to 5.5 v to the vcc1 and vcc2 pins and 0 v to the v ss pin. the vcc apply conditio n is that vcc1 = vcc2. analog power supply input avcc avss i applies the power supply for the a/d converter. connect the avcc pin to vcc1. connect the avss pin to vss. reset input reset i the microcomputer is in a reset state when applying ?l? to the this pin. cnvss cnvss i switches processor mode. c onnect this pin to vss to when after a reset to start up in single-chip mode. connect this pin to vcc1 to start up in microprocessor mode. external data bus width select input byte i switches the data bus in extern al memory space. the data bus is 16 bits long when the this pin is held "l" and 8 bits long when the this pin is held "h". set it to either one. connect this pin to vss when an single-chip mode. bus control pins d0 to d7 i/o inputs and outputs data (d0 to d7) when these pins are set as the separate bus. d8 to d15 i/o inputs and outputs data (d 8 to d15) when external 16-bit data bus is set as the separate bus. a0 to a19 o output address bits (a0 to a19). cs0 to cs3 o output cs0 to cs3 signals. cs0 to cs3 are chip-select signals to specify an external space. wrl /wr wrh /bhe rd o output wrl , wrh , (wr , bhe ), rd signals. wrl and wrh or bhe and wr can be switched by program. ? wrl , wrh and rd are selected the wrl signal becomes "l" by writing data to an even address in an external memory space. the wrh signal becomes "l" by writing data to an odd address in an external memory space. the rd pin signal becomes "l" by reading data in an external memory space. ? wr , bhe and rd are selected the wr signal becomes "l" by writing dat a in an external memory space. the rd signal becomes "l" by reading dat a in an external memory space. the bhe signal becomes "l" by accessing an odd address. select wr , bhe and rd for an external 8-bit data bus. ale o ale is a signal to latch the address. hold i while the hold pin is held "l", the microcomputer is placed in a hold state. hlda o in a hold state, hlda outputs a "l" signal. rdy i while applying a "l" signal to the rdy pin, the microcomputer is placed in a wait state. m16c/30p group 1. overview rev.1.22 mar 30, 2007 page 13 of 53 rej03b0088-0122 i : input o : output i/o : input and output table 1.9 pin description (2) signal name pin name i/o type description main clock input xin i i/o pins for the main clock generation circuit. connect a ceramic resonator or crystal oscillator between xin and xout. to use the external clock, input the clock from xin and leave xout open. main clock output xout o sub clock input xcin i i/o pins for a sub clock oscillation circuit. connect a crystal oscillator between xcin and xcout. to use the external clock, input the clock from xcin and leave xcout open. sub clock output xcout o clock output clkout o the clock of the same cycle as fc, f8, or f32 is outputted. int interrupt input int0 to int4 i input pins for the int interrupt. nmi interrupt input nmi i input pin for the nmi interrupt. key input interrupt input ki0 to ki3 i input pins for the key input interrupt. timer a ta0out to ta2out i/o these are timer a0 to timer a2 i/o pins. (however, the output of ta0out for the n-channel open drain output.) ta0in to ta2in i these are timer a0 to timer a2 input pins. timer b tb0in to tb2in i these are timer b0 to timer b2 input pins. serial interface cts0 to cts2 i these are send control input pins. rts0 to rts2 o these are receive control output pins. clk0 to clk2 i/o these are transfer clock i/o pins. rxd0 to rxd2 i these are serial data input pins. txd0 to txd2 o these are serial data output pins. (however, txd2 for the n-channel open drain output.) clks1 o this is output pin for transfer clo ck output from multiple pins function. i 2 c mode sda0 to sda2 i/o these are serial data i/o pins. (however, sda2 for the n-channel open drain output.) scl0 to scl2 i/o these are transfer clock i/o pins. (however, scl2 for the n-channel open drain output.) reference voltage input vref i applies the reference voltage for the a/d converter. a/d converter an0 to an7, an0_0 to an0_7 i analog input pins for the a/d converter. adtrg i this is an a/d trigger input pin. anex0 i/o this is the extended analog input pin for the a/d converter, and is the output in external op-amp connection mode. anex1 i this is the extended analog input pin for the a/d converter. i/o port p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p9_0 to p9_7, p10_0 to p10_7 i/o 8-bit i/o ports in cmos, having a direction register to select an input or output. each pin is set as an input port or output port. an input port can be set for a pull-up or for no pull-up in 4-bit unit by program. (however, p7_0 and p7_1 for the n-channel open drain output.) p8_0 to p8_4, p8_6, p8_7 i/o i/o ports having equiva lent functions to p0. input port p8_5 i input pin for the nmi interrupt. pin states can be read by the p8_5 bit in the p8 register. m16c/30p group 2. central processing unit (cpu) rev.1.22 mar 30, 2007 page 14 of 53 rej03b0088-0122 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. there are two register banks. figure 2.1 central processing unit register 2.1 data registers (r 0, r1, r2 and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data registers. r1h and r1l are the same as r0h and r0l. conversely, r2 and r0 can be combined for use as a 32-bit data register (r2r0). r3r1 is the same as r2r0. data registers (1) address registers (1) frame base registers (1) program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register notes: 1. these registers comprise a register bank. there are two register banks. r0h b15 b8 b7 b0 r3 intbh usp isp sb c d z s b o i u ipl r0l r1h r1l r2 b31 r3 r2 a1 a0 fb b19 intbl b15 b0 pc b19 b0 b15 b0 flg b15 b0 b15 b0 b7 b8 reserved area carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level m16c/30p group 2. central processing unit (cpu) rev.1.22 mar 30, 2007 page 15 of 53 rej03b0088-0122 2.2 address registers (a0 and a1) the register a0 consists of 16 bits, an d is used for address regist er indirect addressing an d address register relative addressing. they also are used for transfers and logic/logic opera tions. a1 is the same as a0. in some instructions, registers a1 and a0 can be co mbined for use as a 32-bit address register (a1a0). 2.3 frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is configured with 20 bits, indicating th e start address of an interrupt vector table. 2.5 program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured wi th 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. 2.7 static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. 2.8 flag register (flg) flg consists of 11 bits, indicating the cpu status. 2.8.1 carry flag (c flag) this flag retains a carry, borrow, or shift-out b it that has occurred in the arithmetic/logic unit. 2.8.2 debug flag (d flag) the d flag is used exclusively for debugging purpose. during normal use, it must be set to ?0?. 2.8.3 zero flag (z flag) this flag is set to ?1? when an arithmetic operation resulted in 0; otherwise, it is ?0?. 2.8.4 sign flag (s flag) this flag is set to ?1? when an arithmetic operation resulted in a nega tive value; otherwise, it is ?0?. 2.8.5 register bank se lect flag (b flag) register bank 0 is selected when this flag is ?0? ; register bank 1 is selected when this flag is ?1?. 2.8.6 overflow flag (o flag) this flag is set to ?1? when the operation resulted in an overflow; otherwise, it is ?0?. 2.8.7 interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabl ed when the i flag is ?0?, and are enab led when the i flag is ?1?. the i flag is cleared to ?0? when the interrupt request is accepted. m16c/30p group 2. central processing unit (cpu) rev.1.22 mar 30, 2007 page 16 of 53 rej03b0088-0122 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is ?0?; usp is selected when the u flag is ?1?. the u flag is cleared to ?0? when a hardware interrupt request is accepte d or an int instru ction for software interrupt nos. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor in terrupt priority le vels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt is enabled. 2.8.10 reserved area when write to this bit, write ?0?. when read, its content is indeterminate. m16c/30p group 3. memory rev.1.22 mar 30, 2007 page 17 of 53 rej03b0088-0122 3. memory figure 3.1 is a memory map of the m16c/30p group. th e address space extends the 1 mbyte from address 00000h to fffffh. the internal rom is allocated in a lower address directio n beginning with address ffff fh. for example, a 64-kbyte internal rom is allocated to the addresses from f0000h to fffffh. the fixed interrupt vector table is al located to the addresses from fffdch to fffffh. therefore, store the start address of each inte rrupt routine here. the internal ram is allocated in an upper address direction beginning with address 00400h. for example, a 5-kbyte internal ram is allocated to the addresses from 00400h to 017ffh. in addition to storing data, the internal ram also stores the stack used when cal ling subroutines and when inte rrupts are generated. the sfr is allocated to the addresses from 00000h to 003ffh. peripheral function control regi sters are located here. of the sfr, any area which has no functions allocated is reserved for future use and cannot be used by users. the special page vector table is allocat ed to the addresses from ffe00h to ff fdbh. this vector is used by the jmps or jsrs instruction. for details, refer to the m16c/60 and m16c/20 s eries software manual . figure 3.1 memory map 00000h xxxxxh external area internal rom (program area) (5) sfr internal ram reserved area (1) reserved area (2, 4) fffdch notes: 1. during memory expansion and microprocessor modes, can be used. 2. in memory expansion mode, can be used. 3. as for the flash memory version, 4-kbyte space (block a) exists. 4. shown here is a memory map for the case where the pm10 bit in the pm1 register is ?1? . 5. when using the masked rom version, write nothing to internal rom area. 6. when the pm13 bit is set to "0", the address of internal rom becomes d0000h, and when the pm13 bit is set to "1", the address becomes c0000h. undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc nmi reserved area external area 00400h 10000h 27000h 28000h d0000h yyyyyh fffffh ffe00h fffffh internal rom (data area) (3, 4) 0ffffh 0f000h 01bffh 017ffh address xxxxxh 6 kbytes 5 kbytes size address yyyyyh size e8000h e0000h 128 kbytes 96 kbytes d8000h 160 kbytes 192 kbytes d0000h internal ram internal rom (5) 256 kbytes c0000h (6) 033ffh 12 kbytes m16c/30p group 4. special function register (sfr) rev.1.22 mar 30, 2007 page 18 of 53 rej03b0088-0122 4. special function register (sfr) sfr(special function register) is the c ontrol register of peripheral functions. tables 4.1 to 4.5 list the sfr information. notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. the pm00 and pm01 bits do not change at software reset. x : nothing is mapped to this bit table 4.1 sfr information (1) (1) address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 (2) pm0 00000000b(cnvss pin is ?l?) 00000011b(cnvss pin is ?h?) 0005h processor mode register 1 pm1 00xxx0x0b 0006h system clock control register 0 cm0 01001000b 0007h system clock control register 1 cm1 00100000b 0008h chip select control register csr 00000001b 0009h address match interrupt enable register aier xxxxxx00b 000ah protect register prcr xx000000b 000bh 000ch 000dh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00xxxxxxb 0010h address match interrupt register 0 rmad0 00h 0011h 00h 0012h x0h 0013h 0014h address match interrupt register 1 rmad1 00h 0015h 00h 0016h x0h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh 0020h dma0 source pointer sar0 xxh 0021h xxh 0022h xxh 0023h 0024h dma0 destination pointer dar0 xxh 0025h xxh 0026h xxh 0027h 0028h dma0 transfer counter tcr0 xxh 0029h xxh 002ah 002bh 002ch dma0 control register dm0con 00000x00b 002dh 002eh 002fh 0030h dma1 source pointer sar1 xxh 0031h xxh 0032h xxh 0033h 0034h dma1 destination pointer dar1 xxh 0035h xxh 0036h xxh 0037h 0038h dma1 transfer counter tcr1 xxh 0039h xxh 003ah 003bh 003ch dma1 control register dm1con 00000x00b 003dh 003eh 003fh m16c/30p group 4. special function register (sfr) rev.1.22 mar 30, 2007 page 19 of 53 rej03b0088-0122 table 4.2 sfr information (2) (1) notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. this register is included in the flash memory version. 3. this register is included in the flash memory version and one time flash version. x : nothing is mapped to this bit address register symbol after reset 0040h 0041h 0042h 0043h 0044h int3 interrupt control register int3ic xx00x000b 0045h 0046h uart1 bus collision detection interrupt control register u1bcnic xxxxx000b 0047h uart0 bus collision detection interrupt control register u0bcnic xxxxx000b 0048h 0049h int4 interrupt control register int4ic xx00x000b 004ah uart2 bus collision detection interrupt control register bcnic xxxxx000b 004bh dma0 interrupt control register dm0ic xxxxx000b 004ch dma1 interrupt control register dm1ic xxxxx000b 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh uart2 transmit interrupt control register s2tic xxxxx000b 0050h uart2 receive interrupt control register s2ric xxxxx000b 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h timer a0 interrupt control register ta0ic xxxxx000b 0056h timer a1 interrupt control register ta1ic xxxxx000b 0057h timer a2 interrupt control register ta2ic xxxxx000b 0058h 0059h 005ah timer b0 interrupt control register tb0ic xxxxx000b 005bh timer b1 interrupt control register tb1ic xxxxx000b 005ch timer b2 interrupt control register tb2ic xxxxx000b 005dh int0 interrupt control register int0ic xx00x000b 005eh int1 interrupt control register int1ic xx00x000b 005fh int2 interrupt control register int2ic xx00x000b 0060h to 01afh 01b0h 01b1h 01b2h 01b3h 01b4h 01b5h flash memory control register 1 (2) fmr1 0x00xx0xb 01b6h 01b7h flash memory control register 0 (3) fmr0 00000001b 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh 01c0h to 024fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025ah 025bh 025ch 025dh 025eh peripheral clock select register pclkr 00000011b 025fh 0260h to 033fh m16c/30p group 4. special function register (sfr) rev.1.22 mar 30, 2007 page 20 of 53 rej03b0088-0122 table 4.3 sfr information (3) (1) notes: 1. the blank areas are reserved an d cannot be accessed by users. x : nothing is mapped to this bit address register symbol after reset 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034ah 034bh 034ch 034dh 034eh 034fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035ah 035bh 035ch 035dh 035eh interrupt factor select register 2 ifsr2a 00xxxxxxb 035fh interrupt factor select register ifsr 00h 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036ah 036bh 036ch uart0 special mode register 4 u0smr4 00h 036dh uart0 special mode register 3 u0smr3 000x0x0xb 036eh uart0 special mode register 2 u0smr2 x0000000b 036fh uart0 special mode register u0smr x0000000b 0370h uart1 special mode register 4 u1smr4 00h 0371h uart1 special mode register 3 u1smr3 000x0x0xb 0372h uart1 special mode register 2 u1smr2 x0000000b 0373h uart1 special mode register u1smr x0000000b 0374h uart2 special mode register 4 u2smr4 00h 0375h uart2 special mode register 3 u2smr3 000x0x0xb 0376h uart2 special mode register 2 u2smr2 x0000000b 0377h uart2 special mode register u2smr x0000000b 0378h uart2 transmit/receive mode register u2mr 00h 0379h uart2 bit rate generator u2brg xxh 037ah uart2 transmit buffer register u2tb xxh 037bh xxh 037ch uart2 transmit/receive control register 0 u2c0 00001000b 037dh uart2 transmit/receive control register 1 u2c1 00000010b 037eh uart2 receive buffer register u2rb xxh 037fh xxh m16c/30p group 4. special function register (sfr) rev.1.22 mar 30, 2007 page 21 of 53 rej03b0088-0122 table 4.4 sfr information (4) (1) notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. bit 5 in the up-down flag is ?0? by reset. however, the values in these bits when read are indeterminate. x : nothing is mapped to this bit address register symbol after reset 0380h count start flag tabsr 000xx000b 0381h clock prescaler reset fag cpsrf 0xxxxxxxb 0382h one-shot start flag onsf 00xxx000b 0383h trigger select register trgsr xxxx0000b 0384h up-down flag udf xx0xx000b (2) 0385h 0386h timer a0 register ta0 xxh 0387h xxh 0388h timer a1 register ta1 xxh 0389h xxh 038ah timer a2 register ta2 xxh 038bh xxh 038ch 038dh 038eh 038fh 0390h timer b0 register tb0 xxh 0391h xxh 0392h timer b1 register tb1 xxh 0393h xxh 0394h timer b2 register tb2 xxh 0395h xxh 0396h timer a0 mode register ta0mr 00h 0397h timer a1 mode register ta1mr 00h 0398h timer a2 mode register ta2mr 00h 0399h 039ah 039bh timer b0 mode register tb0mr 00xx0000b 039ch timer b1 mode register tb1mr 00xx0000b 039dh timer b2 mode register tb2mr 00xx0000b 039eh 039fh 03a0h uart0 transmit/receive mode register u0mr 00h 03a1h uart0 bit rate generator u0brg xxh 03a2h uart0 transmit buffer register u0tb xxh 03a3h xxh 03a4h uart0 transmit/receive control register 0 u0c0 00001000b 03a5h uart0 transmit/receive control register 1 u0c1 00000010b 03a6h uart0 receive buffer register u0rb xxh 03a7h xxh 03a8h uart1 transmit/receive mode register u1mr 00h 03a9h uart1 bit rate generator u1brg xxh 03aah uart1 transmit buffer register u1tb xxh 03abh xxh 03ach uart1 transmit/receive control register 0 u1c0 00001000b 03adh uart1 transmit/receive control register 1 u1c1 00000010b 03aeh uart1 receive buffer register u1rb xxh 03afh xxh 03b0h uart transmit/receive control register 2 ucon x0000000b 03b1h 03b2h 03b3h 03b4h 03b5h 03b6h 03b7h 03b8h dma0 request factor select register dm0sl 00h 03b9h 03bah dma1 request factor select register dm1sl 00h 03bbh 03bch crc data register crcd xxh 03bdh xxh 03beh crc input register crcin xxh 03bfh m16c/30p group 4. special function register (sfr) rev.1.22 mar 30, 2007 page 22 of 53 rej03b0088-0122 table 4.5 sfr information (5) (1) notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. at hardware reset, the register is as follows: ? ?00000000b? where ?l? is inputted to the cnvss pin ? ?00000010b? where ?h? is inputted to the cnvss pin at software reset, the register is as follows: ? ?00000000b? where the pm01 to pm00 bits in the pm0 register are ?00b? (single-chip mode). ? ?00000010b? where the pm01 to pm00 bits in the pm0 register are ?01b? (memory expansion mode) or ?11b? (microprocessor mode) . x : nothing is mapped to this bit address register symbol after reset 03c0h a/d register 0 ad0 xxh 03c1h xxh 03c2h a/d register 1 ad1 xxh 03c3h xxh 03c4h a/d register 2 ad2 xxh 03c5h xxh 03c6h a/d register 3 ad3 xxh 03c7h xxh 03c8h a/d register 4 ad4 xxh 03c9h xxh 03cah a/d register 5 ad5 xxh 03cbh xxh 03cch a/d register 6 ad6 xxh 03cdh xxh 03ceh a/d register 7 ad7 xxh 03cfh xxh 03d0h 03d1h 03d2h 03d3h 03d4h a/d control register 2 adcon2 xxx000x0b 03d5h 03d6h a/d control register 0 adcon0 000x0xxxb 03d7h a/d control register 1 adcon1 00000xxxb 03d8h 03d9h 03dah 03dbh 03dch 03ddh 03deh 03dfh 03e0h port p0 register p0 xxh 03e1h port p1 register p1 xxh 03e2h port p0 direction register pd0 00h 03e3h port p1 direction register pd1 00h 03e4h port p2 register p2 xxh 03e5h port p3 register p3 xxh 03e6h port p2 direction register pd2 00h 03e7h port p3 direction register pd3 00h 03e8h port p4 register p4 xxh 03e9h port p5 register p5 xxh 03eah port p4 direction register pd4 00h 03ebh port p5 direction register pd5 00h 03ech port p6 register p6 xxh 03edh port p7 register p7 xxh 03eeh port p6 direction register pd6 00h 03efh port p7 direction register pd7 00h 03f0h port p8 register p8 xxh 03f1h port p9 register p9 xxh 03f2h port p8 direction register pd8 00x00000b 03f3h port p9 direction register pd9 00h 03f4h port p10 register p10 xxh 03f5h 03f6h port p10 direction register pd10 00h 03f7h 03f8h 03f9h 03fah 03fbh 03fch pull-up control register 0 pur0 00h 03fdh pull-up control register 1 pur1 00000000b (2) 00000010b (2) 03feh pull-up control register 2 pur2 00h 03ffh port control register pcr 00h m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 23 of 53 rej03b0088-0122 5. electrical characteristics table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc supply voltage(v cc1 =v cc2 )v cc1 =v cc2 =av cc ? 0.3 to 6.5 v av cc analog supply voltage v cc1 =v cc2 =av cc ? 0.3 to 6.5 v v i input voltage reset , cnvss, byte, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, vref, xin ? 0.3 to v cc +0.3 v p7_0, p7_1 ? 0.3 to 6.5 v v o output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7, xout ? 0.3 to v cc +0.3 v p7_0, p7_1 ? 0.3 to 6.5 v p d power dissipation ? 40 c m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 25 of 53 rej03b0088-0122 notes: 1. referenced to v cc =av cc =v ref =3.3 to 5.5v, v ss =av ss =0v at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified. 2. ad frequency must be 10 mhz or less. 3. when sample & hold function is disabled, ad frequency must be 250 khz or more, in addition to the limitation in note 2. 4. when sample & hold function is enabled, ad frequency must be 1mhz or more, in addition to the limitation in note 2. table 5.3 a/d conversion characteristics (1) symbol parameter measuring condition standard unit min. typ. max. ? resolution v ref =v cc 10 bits inl integral non-linearity error 10bit v ref = v cc = 5v an0 to an7 input, an0_0 to an0_7 input, anex0, anex1 input 5 lsb v ref = v cc = 3.3v an0 to an7 input, an0_0 to an0_7 input, anex0, anex1 input 7 lsb 8bit v ref =v cc =5v, 3.3v 2 lsb ? absolute accuracy 10bit v ref = v cc = 5v an0 to an7 input, an0_0 to an0_7 input, anex0, anex1 input 5 lsb v ref = v cc =3.3v an0 to an7 input, an0_0 to an0_7 input, anex0, anex1 input 7 lsb 8bit v ref =v cc =5v, 3.3v 2 lsb ? tolerance level impedance 3 k dnl differential non-linearity error 2 lsb ? offset error 5 lsb ? gain error 5 lsb r ladder ladder resistance v ref =v cc 10 40 k t conv 10-bit conversion time, sample & hold function available v ref =v cc =5v, ad=10mhz 3.3 s t conv 8-bit conversion time, sample & hold function available v ref =v cc =5v, ad=10mhz 2.8 s t samp sampling time 0.3 s v ref reference voltage 3.0 v cc v v ia analog input voltage 0 v ref v m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 26 of 53 rej03b0088-0122 notes: 1. referenced to v cc1 =4.5 to 5.5v, 3.0 to 3.6v at topr = 0 to 60 c (u3, u5) unless otherwise specified. 2. program and erase endurance refers to the number of times a block erase can be performed. if the program and erase endurance is 1 00, each block can be erased 100 times. for example, if a 4 kbytes block a is er ased after writing 1 word data 2,048 times, each to a different address, this counts as one program and erase endurance. data cannot be written to t he same address more than once without erasing the block. (rewrite prohibited) 3. maximum number of e/w cycles for which operation is guaranteed. 4. topr = -40 to 85 c (u3) / -20 to 85 c (u5). table 5.4 flash memory version electrical characteristics (1) symbol parameter standard unit min. typ. max. ? program and erase endurance (2) 100 (3) cycle ? word program time (v cc1 =5.0v ) 25 200 s ? lock bit program time 25 200 s ? block erase time (v cc1 =5.0v ) 4-kbyte block 0.3 4 s ? 8-kbyte block 0.3 4 s ? 32-kbyte block 0.5 4 s ? 64-kbyte block 0.8 4 s t ps flash memory circuit stabilization wait time 15 s ? data hold time (4) 10 year table 5.5 flash memory version program / erase voltage and read operation voltage characteristics flash program, erase voltage flash read operation voltage v cc1 = 3.3 0.3 v or 5.0 0.5 ( t opr = 0 c to 60 c ) v cc1 =2.7 to 5.5 v ( t opr = -40 c to 85 c (u3) -20 c to 85 c (u5)) m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 27 of 53 rej03b0088-0122 notes: 1. referenced to v cc1 =4.5 to 5.5v, 3.0 to 3.6v at topr = 0 to 60 c (u3, u5) unless otherwise specified. 2. topr = -40 to 85 c (u3) / -20 to 85 c (u5). table 5.6 one time flash versi on electrical characteristics (1) symbol parameter standard unit min. typ. max. ? program endurance 1cycle ? word program time (v cc1 =5.0v ) 50 500 s tps one time flash memory circuit stabilization wait time 15 s ? data hold time (4) 10 year table 5.7 one time flash version program voltage and read operation voltage characteristics flash program voltage flash read operation voltage v cc1 = 3.3 0.3 v or 5.0 0.5 ( t opr = 0 c to 60 c ) v cc1 =2.7 to 5.5 v ( t opr = -40 c to 85 c (u3) -20 c to 85 c (u5)) m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 28 of 53 rej03b0088-0122 figure 5.1 power supply circuit timing diagram table 5.8 power supply circuit timing characteristics symbol parameter measuring condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during powering-on v cc =2.7v to 5.5v 2 ms t d(r-s) stop release time 1500 s t d(w-s) low power dissipation mode wait mode release time 1500 s t d(p-r) v cc cpu clock cpu clock t d(r-s) (a) (b) t d(w-s) td(p-r) time for internal power supply stabilization during powering-on interrupt for (a) stop mode release or (b)wait mode release td(r-s) stop release time td(w-s) low power dissipation mode wait mode release time recommended operation voltage m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 29 of 53 rej03b0088-0122 v cc1 =v cc2 =5v notes: 1. referenced to v cc1 =v cc2 =4.2 to 5.5v, v ss = 0v at t opr = ? 20 to 85 c / ? 40 to 85 c, f(xin) =16mhz unless otherwise specified. table 5.9 electrical characteristics(1) (1) symbol parameter measuring condition standard unit min. typ. max. v oh high output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 i oh = ? 5ma v cc ? 2.0 v cc v v oh high output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 i oh = ? 200 a v cc ? 0.3 v cc v v oh high output voltage xout highpower i oh = ? 1ma v cc ? 2.0 v cc v lowpower i oh = ? 0.5ma v cc ? 2.0 v cc high output voltage xcout highpower with no load applied 2.5 v lowpower with no load applied 1.6 v ol low output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 i ol =5ma 2.0 v v ol low output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 i ol =200 a 0.45 v v ol low output voltage xout highpower i ol =1ma 2.0 v lowpower i ol =0.5ma 2.0 low output voltage xcout highpower with no load applied 0 v lowpower with no load applied 0 v t+- v t- hysteresis ta0in to ta2in, tb0in to tb2in, int0 to int4 , nmi , adtrg , cts0 to cts2 , clk0 to clk2, ta0out to ta2out, ki0 to ki3 , rxd0 to rxd2, scl0 to scl2, sda0 to sda2 0.2 1.0 v v t+- v t- hysteresis reset 0.2 2.5 v i ih high input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset , cnvss, byte v i =5v 5.0 a i il low input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset , cnvss, byte v i =0v ? 5.0 a r pullup pull-up resistance p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 v i =0v 30 50 170 k r fxin feedback resistance xin 1.5 m r fxcin feedback resistance xcin 15 m v ram ram retention voltage at stop mode 2.0 v m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 30 of 53 rej03b0088-0122 notes: 1. referenced to v cc1 =v cc2 =4.2 to 5.5v, v ss = 0v at t opr = ? 20 to 85 c / ? 40 to 85 c, f(xin)=16mhz unless otherwise specified. 2. with one timer operated using fc32. 3. this indicates the memory in which the program to be executed exists. table 5.10 electrical characteristics (2) (1) symbol parameter measuring condition standard unit min. typ. max. i cc power supply current (v cc1 =v cc2 =4.0v to 5.5v) in single-chip mode, the output pins are open and other pins are v ss mask rom f(xin)=16mhz no division 10 15 ma one time flash f(xin)=16mhz, no division 10 18 ma flash memory f(xin)=16mhz, no division 12 18 ma one time flash f(xin)=10mhz, vcc1=5.0v 15 ma flash memory program f(xin)=10mhz, vcc1=5.0v 15 ma flash memory erase f(xin)=10mhz, vcc1=5.0v 25 ma mask rom f(xcin)=32khz low power dissipation mode, rom (3) 25 a one time flash f(xcin)=32khz low power dissipation mode, ram (3) 25 a f(xcin)=32khz low power dissipation mode, flash memory (3) 350 a flash memory f(xcin)=32khz low power dissipation mode, ram (3) 25 a f(xcin)=32khz low power dissipation mode, flash memory (3) 420 a mask rom one time flash flash memory f(xcin)=32khz wait mode (2) , oscillation capability high 7.5 a f(xcin)=32khz wait mode (2) , oscillation capability low 2.0 a stop mode topr =25 c 0.8 3.0 a m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 31 of 53 rej03b0088-0122 v cc1 =v cc2 =5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. the condition is v cc1 =v cc2 =3.0 to 5.0v. notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: n is ?2? for 1-wait setting. table 5.11 external clock input (xin input) (1) symbol parameter standard unit min. max. t c external clock input cycle time 62.5 ns t w(h) external clock input high pulse width 25 ns t w(l) external clock input low pulse width 25 ns t r external clock rise time 15 ns t f external clock fall time 15 ns table 5.12 memory expansion mode and microprocessor mode symbol parameter standard unit min. max. t ac1(rd-db) data input access time (for setting with no wait) (note 1) ns t ac2(rd-db) data input access time (for setting with wait) (note 2) ns t su(db-rd) data input setup time 40 ns t su(rdy-bclk) rdy input setup time 30 ns t su(hold-bclk) hold input setup time 40 ns t h(rd-db) data input hold time 0 ns t h(bclk-rdy) rdy input hold time 0 ns t h(bclk-hold) hold input hold time 0 ns 0.5x10 9 fbclk () ----------------------- -45ns [] ? n0.5 ? () x 10 9 fbclk () ------------------------------------ -45ns [] ? m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 32 of 53 rej03b0088-0122 v cc1 =v cc2 =5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 5.13 timer a input (counter input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 100 ns t w(tah) taiin input high pulse width 40 ns t w(tal) taiin input low pulse width 40 ns table 5.14 timer a input (gating input in timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 400 ns t w(tah) taiin input high pulse width 200 ns t w(tal) taiin input low pulse width 200 ns table 5.15 timer a input (external trigger input in one-shot timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 200 ns t w(tah) taiin input high pulse width 100 ns t w(tal) taiin input low pulse width 100 ns table 5.16 timer a input (external trigger input in pulse width modulation mode) symbol parameter standard unit min. max. t w(tah) taiin input high pulse width 100 ns t w(tal) taiin input low pulse width 100 ns table 5.17 timer a input (counter increment/ decrement input in event counter mode) symbol parameter standard unit min. max. t c(up) taiout input cycle time 2000 ns t w(uph) taiout input high pulse width 1000 ns t w(upl) taiout input low pulse width 1000 ns t su(up-tin) taiout input setup time 400 ns t h(tin-up) taiout input hold time 400 ns table 5.18 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 800 ns t su(tain-taout) taiout input setup time 200 ns t su(taout-tain) taiin input setup time 200 ns m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 33 of 53 rej03b0088-0122 v cc1 =v cc2 =5v timing requirements (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 5.19 timer b input (counter input in event counter mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time (counted on one edge) 100 ns t w(tbh) tbiin input high pulse width (counted on one edge) 40 ns t w(tbl) tbiin input low pulse width (counted on one edge) 40 ns t c(tb) tbiin input cycle time (counted on both edges) 200 ns t w(tbh) tbiin input high pulse width (counted on both edges) 80 ns t w(tbl) tbiin input low pulse width (counted on both edges) 80 ns table 5.20 timer b input (pulse period measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 400 ns t w(tbh) tbiin input high pulse width 200 ns t w(tbl) tbiin input low pulse width 200 ns table 5.21 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 400 ns t w(tbh) tbiin input high pulse width 200 ns t w(tbl) tbiin input low pulse width 200 ns table 5.22 a/d trigger input symbol parameter standard unit min. max. t c(ad) adtrg input cycle time 1000 ns t w(adl) adtrg input low pulse width 125 ns table 5.23 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ns t w(ckh) clki input high pulse width 100 ns t w(ckl) clki input low pulse width 100 ns t d(c-q) txdi output delay time 80 ns t h(c-q) txdi hold time 0 ns t su(d-c) rxdi input setup time 70 ns t h(c-d) rxdi input hold time 90 ns table 5.24 external interrupt inti input symbol parameter standard unit min. max. t w(inh) inti input high pulse width 250 ns t w(inl) inti input low pulse width 250 ns m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 34 of 53 rej03b0088-0122 v cc1 =v cc2 =5v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to the bclk frequency as follows: f(bclk) is 12.5mhz or less. 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies wi th capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr x ln (1 ? v ol / v cc1 ) by a circuit of the right figure. for example, when v ol = 0.2v cc1 , c = 30pf, r = 1k , hold time of output ?l? level is t = ? 30pf x 1k x in(1 ? 0.2v cc1 / v cc1 ) = 6.7ns. figure 5.2 ports p0 to p10 measurement circuit table 5.25 memory expansion and micropro cessor modes (for setting with no wait) symbol parameter standard unit min. max. t d(bclk-ad) address output delay time see figure 5.2 25 ns t h(bclk-ad) address output hold time (in relation to bclk) ? 3ns t h(rd-ad) address output hold time (in relation to rd) 0 ns t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 25 ns t h(bclk-cs) chip select output hold time (in relation to bclk) ? 3ns t d(bclk-ale) ale signal output delay time 15 ns t h(bclk-ale) ale signal output hold time ? 4ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 4ns t d(db-wr) data output delay time (in relation to wr) (note 1) ns th(wr-db) data output hold time (in relation to wr) (3) (note 2) ns t d(bclk-hlda) hlda output delay time 40 ns 0.5x10 9 fbclk () ----------------------- -40ns [] ? 0.5x10 9 fbclk () ----------------------- -10ns [] ? dbi r c p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 35 of 53 rej03b0088-0122 v cc1 =v cc2 =5v switching characteristics (v cc1 = v cc2 = 5v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to the bclk frequency as follows: n is ?1? for 1-wait setting, f(bclk) is 12.5mhz or less. 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies wi th capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr x ln (1 ? v ol / v cc1 ) by a circuit of the right figure. for example, when v ol = 0.2v cc1 , c = 30pf, r = 1k , hold time of output ?l? level is t = ? 30pf x 1k x in(1 ? 0.2v cc1 / v cc1 ) = 6.7ns. table 5.26 memory expansion and microprocessor modes (for 1 wait setting and external area access) symbol parameter standard unit min. max. t d(bclk-ad) address output delay time see figure 5.2 25 ns t h(bclk-ad) address output hold time (in relation to bclk) ? 3ns t h(rd-ad) address output hold time (in relation to rd) 0 ns t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 25 ns t h(bclk-cs) chip select output hold time (in relation to bclk) ? 3ns t d(bclk-ale) ale signal output delay time 15 ns t h(bclk-ale) ale signal output hold time ? 4ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 4ns t d(db-wr) data output delay time (in relation to wr) (note 1) ns th(wr-db) data output hold time (in relation to wr) (3) (note 2) ns t d(bclk-hlda) hlda output delay time 40 ns n0.5 ? () x10 9 fbclk () ------------------------------------ 4 0 n s [] ? 0.5x10 9 fbclk () ----------------------- -10ns [] ? dbi r c m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 36 of 53 rej03b0088-0122 figure 5.3 timing diagram (1) taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on fa lling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c v cc1 =v cc2 =5v m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 37 of 53 rej03b0088-0122 figure 5.4 timing diagram (2) t su(d-c) clk i txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) int i input t d(c-q) t h(c-d) t h(c-q) v cc1 =v cc2 =5v m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 38 of 53 rej03b0088-0122 figure 5.5 timing diagram (3) memory expansion mode, microprocessor mode ( effective for setting with wait ) bclk hold input hlda input measuring conditions : v cc1 =v cc2 =5v input timing voltage : determined with v il =1.0v, v ih =4.0v output timing voltage : determined with v ol =2.5v, v oh =2.5v p0, p1, p2, p3, p4, p5_0 to p5_2 (1) ( common to setting with wait and setting without wait ) notes: 1. these pins are set to high-impedance regardless of the input level of the byte pin, pm06 bit in pm0 register. t h(bclk ? hold) t su(hold ? bclk) t d(bclk ? hlda) t d(bclk ? hlda) hi ? z rdy input t su(rdy ? bclk) t h(bclk ? rdy) rd bclk (separate bus) wr, wrl, wrh (separate bus) v cc1 =v cc2 =5v m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 39 of 53 rej03b0088-0122 figure 5.6 timing diagram (4) bclk csi t d(bclk-cs) 25ns.max adi 25ns.max ale 25ns.max -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) ? 3ns.min t h(bclk-cs) ? 3ns.min hi-z dbi t h(rd-db) 0ns.min 0ns.min t h(rd-ad) bhe t cyc read timing t d(bclk-ad) t d(bclk-ale) t h(bclk-ale) t su(db-rd) t d(bclk-rd) 40ns.min t ac1(rd-db) memory expansion mode, microprocessor mode ( for setting with no wait ) measuring conditions v cc1 =v cc2 =5v input timing voltage : v il =0.8v, v ih =2.0v output timing voltage : v ol =0.4v, v oh =2.4v wr, wrl, wrh 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) ? 3ns.min t h(bclk-cs) ? 3ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 t cyc -40)ns.min t h(wr-db) dbi write timing t d(bclk-wr) hi-z (0.5 t cyc -45)ns.max t cyc = 1 f(bclk) (0.5 t cyc -10)ns.min (0.5 t cyc -10)ns.min v cc1 =v cc2 =5v m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 40 of 53 rej03b0088-0122 figure 5.7 timing diagram (5) bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t h(bclk-ale) -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) ? 3ns.min t h(bclk-cs) ? 3ns.min hi-z dbi t su(db-rd) 40ns.min t h(rd-db) 0ns.min t cyc bhe read timing wr, wrl, wrh 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) ? 3ns.min t h(bclk-cs) ? 3ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 t cyc -40)ns.min (0.5 t cyc -10)ns.min t h(wr-db) dbi write timing t d(bclk-ale) t d(bclk-rd) t d(bclk-wr) 0ns.min t h(rd-ad) t ac2(rd-db) hi-z memory expansion mode , microprocessor mode ( for 1-wait setting and external area access ) measuring conditions v cc1 =v cc2 =5v input timing voltage : v il =0.8v, v ih =2.0v output timing voltage : v ol =0.4v, v oh =2.4v (1.5 t cyc -45)ns.max t cyc = f(bclk) 1 (0.5 tcyc-10)ns.min v cc1 =v cc2 =5v m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 41 of 53 rej03b0088-0122 v cc1 =v cc2 =3v notes: 1. referenced to v cc1 = v cc2 = 2.7 to 3.3v, v ss = 0v at topr = ? 20 to 85 c / ? 40 to 85 c, f(xin)=10mhz no wait unless otherwise specified. table 5.27 electrical characteristics (1) (1) symbol parameter measuring condition standard unit min. typ. max. v oh high output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 i oh = ? 1ma v cc ? 0.5 v cc v v oh high output voltage xout highpower i oh = ? 0.1ma v cc ? 0.5 v cc v lowpower i oh = ? 50 av cc ? 0.5 v cc high output voltage xcout highpower with no load applied 2.5 v lowpower with no load applied 1.6 v ol low output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 i ol =1ma 0.5 v v ol low output voltage xout highpower i ol =0.1ma 0.5 v lowpower i ol =50 a0.5 low output voltage xcout highpower with no load applied 0 v lowpower with no load applied 0 v t+- v t- hysteresis ta0in to ta2in, tb0in to tb2in, int0 to int4 , nmi , adtrg , cts0 to cts2 , rxd0 to rxd2, clk0 to clk2, ta0out to ta2out, ki0 to ki3 , scl0 to scl2, sda0 to sda2 0.2 0.8 v v t+- v t- hysteresis reset 0.2 (0.7) 1.8 v i ih high input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset , cnvss, byte v i =3v 4.0 a i il low input current p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, xin, reset , cnvss, byte v i =0v ? 4.0 a r pullup pull-up resistance p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 v i =0v 50 100 500 k r fxin feedback resistance xin 3.0 m r fxcin feedback resistance xcin 25 m v ram ram retention voltage at stop mode 2.0 v m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 42 of 53 rej03b0088-0122 notes: 1. referenced to v cc1 =v cc2 =2.7 to 3.3v, v ss = 0v at t opr = ? 20 to 85 c / ? 40 to 85 c, f(xin)=10mhz unless otherwise specified. 2. with one timer operated using fc32. 3. this indicates the memory in which the program to be executed exists. table 5.28 electrical characteristics (2) (1) symbol parameter measuring condition standard unit min. typ. max. i cc power supply current (v cc1 =v cc2 =2.7v to 3.6v) in single-chip mode, the output pins are open and other pins are v ss mask rom f(xin)=10mhz no division 811ma one time flash f(xin)=10mhz, no division 813ma flash memory f(xin)=10mhz, no division 813ma flash memory program f(xin)=10mhz, vcc1=3.0v 12 ma one time flash program f(xin)=10mhz, vcc1=3.0v 12 ma flash memory erase f(xin)=10mhz, vcc1=3.0v 22 ma mask rom f(xcin)=32khz low power dissipation mode, rom (3) 25 a one time flash f(xcin)=32khz low power dissipation mode, ram (3) 25 a f(xcin)=32khz low power dissipation mode, flash memory (3) 350 a flash memory f(xcin)=32khz low power dissipation mode, ram (3) 25 a f(xcin)=32khz low power dissipation mode, flash memory (3) 420 a mask rom one time flash flash memory f(xcin)=32khz wait mode (2) , oscillation capability high 6.0 a f(xcin)=32khz wait mode (2) , oscillation capability low 1.8 a stop mode topr =25 c 0.7 3.0 a m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 43 of 53 rej03b0088-0122 v cc1 =v cc2 =3v timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. the condition is v cc1 =v cc2 =2.7 to 3.0v. 2. calculated according to the v cc1 voltage as follows: [ns] 3. calculated according to the v cc1 voltage as follows: [ns] 4. calculated according to the v cc1 voltage as follows: [ns] notes: 1. calculated according to the bclk frequency as follows: 2. calculated according to the bclk frequency as follows: n is ?2? for 1-wait setting. table 5.29 external clock input (xin input) symbol parameter standard unit min. max. t c external clock input cycle time (note 2) ns t w(h) external clock input high pulse width (note 3) ns t w(l) external clock input low pulse width (note 3) ns t r external clock rise time (note 4) ns t f external clock fall time (note 4) ns table 5.30 memory expansion mode and microprocessor mode symbol parameter standard unit min. max. t ac1(rd-db) data input access time (for setting with no wait) (note 1) ns t ac2(rd-db) data input access time (for setting with wait) (note 2) ns t su(db-rd) data input setup time 50 ns t su(rdy-bclk) rdy input setup time 40 ns t su(hold-bclk) hold input setup time 50 ns t h(rd-db) data input hold time 0 ns t h(bclk-rdy) rdy input hold time 0 ns t h(bclk-hold) hold input hold time 0 ns 10 6 ? 20 v cc1 44 ? --------------------------------------- - 10 6 ? 20 v cc1 44 ? --------------------------------------- - 0.4 10 ? v cc1 45 + 0.5x10 9 fbclk () ----------------------- -60ns [] ? n0.5 ? () x10 9 fbclk () ------------------------------------ 6 0 n s [] ? m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 44 of 53 rej03b0088-0122 v cc1 =v cc2 =3v timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 5.31 timer a input (counter input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 150 ns t w(tah) taiin input high pulse width 60 ns t w(tal) taiin input low pulse width 60 ns table 5.32 timer a input (gating input in timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 600 ns t w(tah) taiin input high pulse width 300 ns t w(tal) taiin input low pulse width 300 ns table 5.33 timer a input (external trigger input in one-shot timer mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 300 ns t w(tah) taiin input high pulse width 150 ns t w(tal) taiin input low pulse width 150 ns table 5.34 timer a input (external trigger input in pulse width modulation mode) symbol parameter standard unit min. max. t w(tah) taiin input high pulse width 150 ns t w(tal) taiin input low pulse width 150 ns table 5.35 timer a input (counter increment/ decrement input in event counter mode) symbol parameter standard unit min. max. t c(up) taiout input cycle time 3000 ns t w(uph) taiout input high pulse width 1500 ns t w(upl) taiout input low pulse width 1500 ns t su(up-tin) taiout input setup time 600 ns t h(tin-up) taiout input hold time 600 ns table 5.36 timer a input (two-phase pulse input in event counter mode) symbol parameter standard unit min. max. t c(ta) taiin input cycle time 2 s t su(tain-taout) taiout input setup time 500 ns t su(taout-tain) taiin input setup time 500 ns m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 45 of 53 rej03b0088-0122 v cc1 =v cc2 =3v timing requirements (v cc1 = v cc2 = 3v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) table 5.37 timer b input (counter input in event counter mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time (counted on one edge) 150 ns t w(tbh) tbiin input high pulse width (counted on one edge) 60 ns t w(tbl) tbiin input low pulse width (counted on one edge) 60 ns t c(tb) tbiin input cycle time (counted on both edges) 300 ns t w(tbh) tbiin input high pulse width (counted on both edges) 120 ns t w(tbl) tbiin input low pulse width (counted on both edges) 120 ns table 5.38 timer b input (pulse period measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 600 ns t w(tbh) tbiin input high pulse width 300 ns t w(tbl) tbiin input low pulse width 300 ns table 5.39 timer b input (pulse width measurement mode) symbol parameter standard unit min. max. t c(tb) tbiin input cycle time 600 ns t w(tbh) tbiin input high pulse width 300 ns t w(tbl) tbiin input low pulse width 300 ns table 5.40 a/d trigger input symbol parameter standard unit min. max. t c(ad) adtrg input cycle time 1500 ns t w(adl) adtrg input low pulse width 200 ns table 5.41 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ns t w(ckh) clki input high pulse width 150 ns t w(ckl) clki input low pulse width 150 ns t d(c-q) txdi output delay time 160 ns t h(c-q) txdi hold time 0 ns t su(d-c) rxdi input setup time 100 ns t h(c-d) rxdi input hold time 90 ns table 5.42 external interrupt inti input symbol parameter standard unit min. max. t w(inh) inti input high pulse width 380 ns t w(inl) inti input low pulse width 380 ns m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 46 of 53 rej03b0088-0122 v cc1 =v cc2 =3v switching characteristics (v cc1 = v cc2 = 3v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to the bclk frequency as follows: f(bclk) is 12.5mhz or less. 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies wi th capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr x ln (1 ? v ol / v cc1 ) by a circuit of the right figure. for example, when v ol = 0.2v cc1 , c = 30pf, r = 1k , hold time of output ?l? level is t = ? 30pf x 1k x in(1 ? 0.2v cc1 / v cc1 ) = 6.7ns. figure 5.8 ports p0 to p10 measurement circuit table 5.43 memory expansion and micropro cessor modes (for setting with no wait) symbol parameter standard unit min. max. t d(bclk-ad) address output delay time see figure 5.8 30 ns t h(bclk-ad) address output hold time (in relation to bclk) 0 ns t h(rd-ad) address output hold time (in relation to rd) 0 ns t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 30 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 0 ns t d(bclk-ale) ale signal output delay time 25 ns t h(bclk-ale) ale signal output hold time ? 4ns t d(bclk-rd) rd signal output delay time 30 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 30 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 4ns t d(db-wr) data output delay time (in relation to wr) (note 1) ns th(wr-db) data output hold time (in relation to wr) (3) (note 2) ns t d(bclk-hlda) hlda output delay time 40 ns 0.5x10 9 fbclk () ----------------------- -40ns [] ? 0.5x10 9 fbclk () ----------------------- -10ns [] ? dbi r c p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 47 of 53 rej03b0088-0122 v cc1 =v cc2 =3v switching characteristics (v cc1 = v cc2 = 3v, v ss = 0v, at t opr = ? 20 to 85 c / ? 40 to 85 c unless otherwise specified) notes: 1. calculated according to the bclk frequency as follows: n is ?1? for 1-wait setting, f(bclk) is 12.5mhz or less. 2. calculated according to the bclk frequency as follows: 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies wi th capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = ? cr x ln (1 ? v ol / v cc1 ) by a circuit of the right figure. for example, when v ol = 0.2v cc1 , c = 30pf, r = 1k , hold time of output ?l? level is t = ? 30pf x 1k x in(1 ? 0.2v cc1 / v cc1 ) = 6.7ns. table 5.44 memory expansion and microprocessor modes (for 1 wait setting and external area access) symbol parameter standard unit min. max. t d(bclk-ad) address output delay time see figure 5.8 30 ns t h(bclk-ad) address output hold time (in relation to bclk) 0 ns t h(rd-ad) address output hold time (in relation to rd) 0 ns t h(wr-ad) address output hold time (in relation to wr) (note 2) ns t d(bclk-cs) chip select output delay time 30 ns t h(bclk-cs) chip select output hold time (in relation to bclk) 0 ns t d(bclk-ale) ale signal output delay time 25 ns t h(bclk-ale) ale signal output hold time -4 ns t d(bclk-rd) rd signal output delay time 30 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 30 ns t h(bclk-wr) wr signal output hold time 0 ns t d(bclk-db) data output delay time (in relation to bclk) 40 ns t h(bclk-db) data output hold time (in relation to bclk) (3) 4ns t d(db-wr) data output delay time (in relation to wr) (note 1) ns th(wr-db) data output hold time (in relation to wr) (3) (note 2) ns t d(bclk-hlda) hlda output delay time 40 ns n0.5 ? () x10 9 fbclk () ------------------------------------ 4 0 n s [] ? 0.5x10 9 fbclk () ----------------------- -10ns [] ? dbi r c m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 48 of 53 rej03b0088-0122 figure 5.9 timing diagram (1) taiin input taiout input during event counter mode tbiin input adtrg input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t h(tin-up) t su(up-tin) taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) taiin input two-phase pulse input in event counter mode t c(ta) t su(tain-taout) t su(taout-tain) t su(tain-taout) t su(taout-tain) taiout input xin input t w(h) t w(l) t r t f t c v cc1 =v cc2 =3v m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 49 of 53 rej03b0088-0122 figure 5.10 timing diagram (2) t su(d-c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) inti input t d(c-q) t h(c-d) t h(c-q) v cc1 =v cc2 =3v m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 50 of 53 rej03b0088-0122 figure 5.11 timing diagram (3) memory expansion mode , microprocessor mode (effective for setting with wait) bclk hold input hlda output measuring conditions : v cc1 =v cc2 =3v input timing voltage : determined with v il =0.6v, v ih =2.4v output timing voltage : determined with v ol =1.5v, v oh =1.5v p0, p1, p2, p3, p4, p5_0 to p5_2 (1) (common to setting with wait and setting without wait) notes: 1. these pins are set to high-impedance regardless of the input level of the byte pin, pm06 bit in pm0 register. t h(bclk ? hold) t su(hold ? bclk) t d(bclk ? hlda) t d(bclk ? hlda) hi ? z rdy input t su(rdy ? bclk) t h(bclk ? rdy) rd bclk (separate bus) wr, wrl, wrh (separate bus) v cc1 =v cc2 =3v m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 51 of 53 rej03b0088-0122 figure 5.12 timing diagram (4) bclk csi t d(bclk-cs) 30ns.max adi 30ns.max ale 30ns.max -4ns.min rd 30ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 0ns.min t h(bclk-cs) 0ns.min hi-z dbi t h(rd-db) 0ns.min 0ns.min t h(rd-ad) bhe t cyc read timing t d(bclk-ad) t d(bclk-ale) t h(bclk-ale) t su(db-rd) t d(bclk-rd) 50ns.min t ac1(rd-db) memory expansion mode, microprocessor mode ( for setting with no wait ) measuring conditions v cc1 =v cc2 =3v input timing voltage : v il =0.6v, v ih =2.4v output timing voltage : v ol =1.5v, v oh =1.5v wr, wrl, wrh 30ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 30ns.max adi t d(bclk-ad) 30ns.max ale 30ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 0ns.min t h(bclk-cs) 0ns.min t cyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 t cyc -40)ns.min t h(wr-db) dbi write timing t d(bclk-wr) hi-z (0.5 t cyc -60)ns.max t cyc = 1 f(bclk) (0.5 t cyc -10)ns.min (0.5 t cyc -10)ns.min v cc1 =v cc2 =3v m16c/30p group 5. electrical characteristics rev.1.22 mar 30, 2007 page 52 of 53 rej03b0088-0122 figure 5.13 timing diagram (5) bclk csi t d(bclk ? cs) 30ns.max adi t d(bclk ? ad) 30ns.max ale 30ns.max t h(bclk ? ale) ? 4ns.min rd 30ns.max t h(bclk ? rd) 0ns.min t h(bclk ? ad) 0ns.min t h(bclk ? cs) 0ns.min hi ? z dbi t su(db ? rd) 50ns.min t h(rd ? db) 0ns.min t cyc bhe read timing wr,wrl, wrh 30ns.max t h(bclk ? wr) 0ns.min bclk csi t d(bclk ? cs) 30ns.max adi t d(bclk ? ad) 30ns.max ale 30ns.max t d(bclk ? ale) t h(bclk ? ale) ? 4ns.min t h(bclk ? ad) 0ns.min t h(bclk ? cs) 0ns.min t cyc t h(wr ? ad) bhe t d(bclk ? db) 40ns.max 4ns.min t h(bclk ? db) t d(db ? wr) (0.5 t cyc ? 40)ns.min (0.5 t cyc ? 10)ns.min t h(wr ? db) dbi write timing t d(bclk ? ale) t d(bclk ? rd) (0.5 t cyc ? 10)ns.min t d(bclk ? wr) 0ns.min t h(rd ? ad) t ac2(rd ? db) hi ? z memory expansion mode, microprocessor mode ( for 1-wait setting and external area access ) (1.5 t cyc ? 60)ns.max t cyc = 1 f(bclk) v cc1 =v cc2 =3v measuring conditions v cc1 =v cc2 =3v input timing voltage : v il =0.6v, v ih =2.4v output timing voltage : v ol =1.5v, v oh =1.5v m16c/30p group appendix 1. package dimensions rev.1.22 mar 30, 2007 page 53 of 53 rej03b0088-0122 appendix 1. package dimensions diagrams showing the latest package dimensions and mounting information ar e available in the "packages" section of the renesas technology website. 0.8 0.5 0.825 0.575 z e z d b p a 1 h e h d y0.10 e0.65 c 0 10 l 0.4 0.6 0.8 0 0.1 0.2 a 3.05 16.5 16.8 17.1 22.5 22.8 23.1 a 2 2.8 e 13.8 14.0 14.2 d 19.8 20.0 20.2 reference symbol dimension in millimeters min nom max 0.25 0.3 0.4 0.13 0.15 0.2 p-qfp100-14x20-0.65 1.6g mass[typ.] 100p6s-a prqp0100jb-a renesas code jeita package code previous code y index mark 100 81 80 51 50 31 30 1 f * 2 * 1 * 3 z e z d e b p a h d d e h e c detail f a 1 a 2 l include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark x 125 26 50 51 75 76 100 f * 1 *3 * 2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y0.08 e0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.914.014.1 d 13.914.014.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e c - 1 revision history m16c/30p group datasheet rev. date description page summary 0.70 aug 26, 2004 ? first edition issued 0.80 mar 18, 2005 ? development support tools -> development tools ? bclk -> cpu clock 2 table 1.1 performance outline of m16c/30p group serial interface is revised. 4 figure 1.2 type., memory size, and package is partly revised. 8 table 1.4 pin detection (2) is partly revised. 20 note 2 table 5.3 a/d conversion characteristics is partly revised. 21 symbol of table 5.4 power supply circu it timing characteristics is partly revised. 22 table 5.5 electrical characteristics is revised. 28 table 5.19 electrical ch aracteristics is revised. 1.00 sep 01, 2005 2 table 1.1 performance outlin e of m16c/30p group is partly revised. 4 table 1.2 product list is partly revised. figure 1.2 type no., memory size, and package is partly revised. 5 figure 1.3 pin configur ation is partly revised. 6 figure 1.4 pin configur ation is partly revised. 7-8 tables 1.3 to 1.4 pin characteristics are added. 9 table 1.5 pin description is revised. 14 3. memory is partly revised. 15 table 4.1 sfr information is partly revised. 19 table 4.5 sfr information is partly revised 21 table 5.2 recommended operating conditions is partly revised. 22 table 5.3 a/d conversion char acteristics is partly revised. 25 note 1 is added in table 5.6 external clock input (xin input) table 5.7 memory expansion mode and microprocessor mode is added. 28 table 5.20 memory expansion mode and microprocessor modes (for setting with no wait) is added. figure 5.2 ports p0 to p10 measurement circuit is added. 29 table 5.21 memory expansion mode and microprocessor modes (for 1- to 3-wait setting and external area access) is added. 32 figure 5.5 timing diagram (3) is added. 33 figure 5.6 timing diagram (4) is added. 34 figure 5.7 timing diagram (5) is added. 36 note 1 to 4 are added in table 5.23 external clock input (xin input) table 5.24 memory expansion mode and microprocessor mode is added. 39 table 5.37 memory expansion mode and microprocessor modes (for setting with no wait) is added. figure 5.8 ports p0 to p10 measurement circuit is added. 40 table 5.38 memory expansion mode and microprocessor modes (for 1- to 3-wait setting and external area access) is added. 43 figure 5.11 timing diagram (3) is added. c - 2 revision history m16c/30p group datasheet 44 figure 5.12 timing diagram (4) is added. 45 figure 5.13 timing diagram (5) is added. 1.10 oct 01, 2005 2 table 1.1 performance outlin e of m16c/30p group is partly revised. 4 table 1.2 product list is partly revised. figure 1.2 type no., memory size, and package is partly revised. 5 table 1.3 product code of mask rom version version for m16c/30p is added. figure 1.3 marking diagram of mask rom version for m16c/30p is added. 6 figure 1.4 marking diagram of rom -less version for m16c/30p is added. 6 table 1.4 product code of rom-less version for m16c/30p is added. 16 figure 3.1 memory map is partly added. 23 table 5.2 information is revised. 1.11 may 31, 2006 4 1.4 product list information is revised. table 1.2 product list is partly revised. 5 figure 1.2 type no., memory size, and package is partly added. 7 table 1.4 product code of flash memory version and rom-less version for m16c/30p is partly revised. figure 1.4 marking diagram of flash memory version and rom-less version for m16c/30p (top view) is partly added. 17 3. memory information is revised. figure 3.1 memory map is partly revised. 18 table 4.1 sfr information( 1) is partly revised. 19 table 4.2 sfr informati on(2) is partly added. 23 table 5.1 absolute maximum ratings information is revised. 26 table 5.4 flash memory version el ectrical characteristics is added. table 5.5 flash memory version program / erase voltage and read operation voltage characteristics is added. 28 table 5.7 electrical characteristics(1) is partly deleted. 29 table 5.8 electrical characteri stics (2) is partly revised. 33 table 5.23 memory expansion and microprocessor modes notes 3 is partly revised. 34 table 5.24 memory expansion and microprocessor modes notes 3 is partly revised. 40 table 5.25 electrical characte ristics (1) is partly deleted. 41 table 5.26 electrical characte ristics (2) is partly revised. 45 table 5.41 memory expansion and microprocessor modes notes 3 is partly revised. 46 table 5.42 memory expansion and microprocessor modes notes 3 is partly revised. rev. date description page summary c - 3 revision history m16c/30p group datasheet 1.20 oct 17, 2006 1 note is partly deleted. 2 table 1.1 performance outline of m16c/30p group is partly added. 4 table 1.2 product list is partly revised. 5 figure 1.2 type no., memory size, and package is added. 7 table 1.4 product code of one time flash version, flash memory ver- sion, and rom-less version for m16c/30p is partly added. 17 figure 3.1 memory map is partly added. 19 table 4.2 sfr information (2) is partly added. 23 table 5.1 absolute maximum ratings is partly added. 27 table 5.6 one time flash versio n electrical characteristics and table 5.7 one time flash version pr ogram voltage and read operation voltage characteristics is added. 30 table 5.10 electrical charac teristics (2) is partly added. 42 table 5.28 electrical charac teristics (2) is partly added. 1.21 nov 02 2006 7 table 1.4 product code of one time flash version, flash memory version, and rom-less version for m16c/30p is partly revised. 1.22 mar 30, 2007 4 table 1.2 produc t list (1) is partly revised. 5 table 1.3 product list (2) is partly revised. 19 table 4.2 sfr information (2) is partly revised. rev. date description page summary notes: 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas product s for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of t he use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this 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